As the semiconductor industry continues to increase performance of integrated circuit devices in accordance with Moore's Law, physical limits of feature size are presenting new challenges to further improvement. For example, transistor gate lengths are approaching a value below which quantum effects cannot be neglected. Without new strategies, such challenges threaten to slow the rate of increase in device performance.
One of these strategies, known as direct silicon bond with hybrid orientation technology (DSB/HOT), results in improved hole mobility for PMOS devices. Another of these strategies, known as strained silicon directly on insulator (sSOI), results in improved electron mobility for NMOS devices. The improvement in electron mobility or hole mobility increases the respective device's speed and overall performance. However, currently these two processes are mutually exclusive.